Pop (tempdata ) join //push and pop together fifo_counter (fifo_counter ) ) initial begin `define BUF_WIDTH 3 module fifo_test () reg clk, rst, wr_en, rd_en reg buf_in reg tempdata wire buf_out wire fifo_counter įifo ff (. Simultaneous push and pop is tested using fork-join once. Observe in the output that we popped the values in the order we pushed.
#FIFO VERILOG CODE BASIC FULL#
Some push and pop are made to test normal full and empty conditions. Selected the bits in these registers same as address width of buffer, whenīuffer overflows, values will overflow and become 0.įollowing testbench can be used to test the fifo code. Rd_ptr and wr_ptr are read and write pointers. Read and write takes place, counter will remain the same.
Will be decremented id read takes place and buffer is not empty. Rd_ptr <= 0 end else begin if ( !buf_full & wr_en ) wr_ptr <= wr_ptr + 1 else wr_ptr <= wr_ptr if ( !buf_empty & rd_en ) rd_ptr <= rd_ptr + 1 else rd_ptr <= rd_ptr end end endmoduleįIFO counter becomes zero or BUF_LENGTH, empty or full flags will beset.įifo_counter is incremented if write takes place and buffer is not full and number of data pushed in to buffer reg buf_out reg buf_empty, buf_full reg fifo_counter reg rd_ptr, wr_ptr // pointer to read and write addresses reg buf_mem // always ) beginīuf_full = (fifo_counter = ` BUF_SIZE ) end always posedge clk or posedge rst ) begin if ( rst )įifo_counter <= 0 else if ( (!buf_full & wr_en ) & ( !buf_empty & rd_en ) )įifo_counter <= fifo_counter else if ( !buf_full & wr_en )įifo_counter <= fifo_counter + 1 else if ( !buf_empty & rd_en )įifo_counter <= fifo_counter end always posedge clk or posedge rst ) begin if ( rst )īuf_out <= 0 else begin if ( rd_en & !buf_empty )īuf_out <= buf_out end end always posedge clk ) begin if ( wr_en & !buf_full )īuf_mem <= buf_mem end always posedge clk or posedge rst ) begin if ( rst ) begin buffer empty and full indication output fifo_counter data input to be pushed to buffer output buf_out of bits to be used in pointer `define BUF_SIZE ( 1 <<` BUF_WIDTH ) module fifo ( clk, rst, buf_in, buf_out, wr_en, rd_en, buf_empty, buf_full, fifo_counter ) input rst, clk, wr_en, rd_en // reset, system clock, write enable and read enable.
`define BUF_WIDTH 3 // BUF_SIZE = 16 -> BUF_WIDTH = 4, no.
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